1. Field of the Invention
The present invention relates to a circuit, and in particular, to an improved address transition detection circuit.
2. Description of the Related Art
As shown in FIG. 1, the conventional address transition detection circuit includes a NOR-gate 10 for operating on an input address AD and a chip selection signal CSb, a latch unit 20 for latching the output from the NOR-gate 10, delay units 30 and 40 for delaying the output from the latch unit 20, and a CMOS flip-flop 50. The CMOS flip-flop 50 is operated by the output from the latch unit 20 for outputting an address transition detection signal ATD in accordance with the outputs from the delay units 30 and 40.
The latch unit 20 includes two input NAND-gates ND1 and ND2 for receiving the inverted output from the NOR-gate 10 and the output from the NOR-gate 10, respectively
The delay unit 30 includes two CMOS inverters I2 and I3 for delaying the output from the NAND-gate ND1, and the delay unit 40 includes two CMOS inverters I4 and I5 for delaying the output from the NAND-gate ND2.
The CMOS flip-flop 50 includes PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2 which are connected in series between a power voltage Vcc and a ground voltage Vss. In addition, PMOS transistors PM3 and PM4 and NMOS transistors NM3 and NM4 are connected in series between the power voltage Vcc and the ground voltage Vss. The output terminal of the CMOS flip-flop 50 is commonly connected to the connection point between the PMOS transistor PM2 and the NMOS transistor NMI, and the connection point between the PMOS transistor PM4 and the NMOS transistor NM3.
The gates of the PMOS transistor PM1 and the NMOS transistor NM4 are connected with the output terminal of the CMOS inverter I3. The gates of the NMOS transistor NM2 and the PMOS transistor PM3 are connected with the output terminal of the CMOS inverter I5. The gates of the PMOS transistor PM2 and the NMOS transistor NM1 are connected with the output terminal of the NAND-gate ND1. The gates of the PMOS transistor PM4 and the NMOS transistor NM3 are connected with the output terminal of the NAND-gate ND2
The operation of the conventional address transition detection circuit will now be explained with reference to FIGS. 2A-2D.
If the chip selection signal CSb is at a low level, when a stable address signal AD as shown in FIG. 2A is inputted, an address transition detection signal ATD having a pulse width corresponding to the delay time by the delay units 30 and 40 is outputted from the CMOS flip-flop 50, as shown in FIG. 2D.
At this time, the stable address signal AD is known as an address signal AD having a pulse width wider than the address transition detection signal ATD.
Namely, if the chip selection signal CSb is at a low level, when a normal address signal AD is transited, the inputs of two NAND-gates ND1 and ND2 of the latch unit 20 has opposite phases.
The NAND-gate which receives a low level signal outputs a high level signal, and another NAND-gate which receives a high level signal outputs a low level signal.
For example, when a normal address signal AD is transited to a high level, the input of the NAND-gate ND1 becomes a high level, and the input of the NAND-gate ND2 becomes a low level As shown in FIG. 2B, the NAND-gates ND1 and ND2 output a low level signal and a high level signal, respectively.
At this time, the PMOS transistor PM2 of the CMOS flip-flop 50 is turned on by a low level signal from the NAND-gate ND1, and the NMOS transistor NM1 is turned off, and the PMOS transistor PM4 is turned off by a high level signal from the NAND-gate ND2, and the NMOS transistor NM3 is turned on.
In addition, the high and low level signals from the NAND-gates ND1 and ND2 are delayed by the delay units 30 and 40 for a predetermined time and are inputted into the CMOS flip-flop 50.
Therefore, the PMOS transistor PM1 is turned on by a low level signal as shown in FIG. 2C, delayed by and outputted from the NAND-gates ND1, and the NMOS transistor NM4 is turned off. Similarly, the NMOS transistor NM2 is turned on, and the PMOS transistor PM3 is turned off. As a result, a high level address transition detection signal ATD, as shown in FIG. 2D, is outputted from the output terminal of the CMOS flip-flop 50.
At this time, the pulse width of the address transition detection signal ATD, which is directly applied to the CMOS flip-flop 50, corresponds with an output time difference between the output signal from the latch unit 20 and the signals delayed by and outputted from the delay units 30 and 40. In other words, the pulse width of the address transition detection signal ATD corresponds with the time delayed by the delay units 30 and 40.
When a short pulse is formed in the address input signal AD due to a noise as shown in FIG. 2A, short pulses, as shown in FIGS. 2B and 2C, occur in the output signals from the NAND-gates ND1 and ND2 of the latch unit 20 and the delay units 30 and 40.
Therefore, the CMOS flip-flop 50, which is controlled by the output signals from the latch unit 20 and the delay units 30 and 40, outputs a short pulse-shaped address transition detection signal ATD as shown in FIG. 2D.
Consequently, it is impossible to obtain a stable operation of the memory device which is operated by the address transition detection signal ATD since the generated short pulse type address transition detection signal ATD becomes smaller than the minimum pulse width which is required for the memory circuit.
In other words, it is possible in the conventional art to obtain a desired address transition detection signal when an address signal having a width wider than the pulse width of the address transition detection signal is inputted. However, it is impossible to obtain a desired address transition detection signal when a short pulse signal having a width narrower than the width of the address transition detection signal, for example, due to a noise, is inputted. Thus, it is impossible to obtain a stable operation of a memory device.